EP2S30F484C3N Altera, EP2S30F484C3N Datasheet - Page 73
![IC STRATIX II FPGA 30K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S30F484C3N
Manufacturer Part Number
EP2S30F484C3N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
No. Of Macrocells
33880
Family Type
Stratix II
No. Of I/o's
342
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
550MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1890
EP2S30F484C3N
EP2S30F484C3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA
Quantity:
591
Part Number:
EP2S30F484C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 73 of 238
- Download datasheet (3Mb)
Altera Corporation
May 2007
Clock pins
CLK12p
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
Enhanced PLL 5 outputs
c0
c1
c2
c3
Top Side Global & Regional
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
of 2)
Clock Network Connectivity
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Stratix II Device Handbook, Volume 1
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Stratix II Architecture
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(Part 1
2–65
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