EP2S60F672I4N Altera, EP2S60F672I4N Datasheet - Page 224
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EP2S60F672I4N
Manufacturer Part Number
EP2S60F672I4N
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1916
EP2S60F672I4N
EP2S60F672I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA
Quantity:
400
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
High-Speed I/O Specifications
5–88
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
H S D R
H S D R D PA
DUTY
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
R I S E
FA L L
Table
Symbol
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
5–89:
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential standards
All differential standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
SPI-4
Parallel Rapid I/O
Miscellaneous
Standard
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
Training
Pattern
Transition
Density
100%
10%
25%
50%
0.44
Min
150
150
256
256
256
256
256
330
(4)
(4)
45
-3 Speed Grade
-
Notes
Typ
50
(1),
Altera Corporation
1,040
1,040
6,400
Max
760
500
200
190
160
180
55
(2)
-
Number of
repetitions
April 2011
Mbps
Mbps
Mbps
Mbps
Unit
ps
ps
ps
ps
ps
UI
UI
%