EP2S60F672I4N Altera, EP2S60F672I4N Datasheet - Page 67
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EP2S60F672I4N
Manufacturer Part Number
EP2S60F672I4N
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1916
EP2S60F672I4N
EP2S60F672I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA
Quantity:
400
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
Table 2–10. Stratix II PLL Features
For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty
cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix II devices can shift all output frequencies in increments of at least 45. Smaller degree
increments are possible depending on the frequency and divide parameters.
Stratix II fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input
per PLL.
Table
Feature
2–10:
Table 2–10
devices.
Down to 125-ps increments (3),
Three differential/six single-ended
One single-ended or differential
m/(n × post-scale counter)
shows the enhanced PLL and fast PLL features in Stratix II
Enhanced PLL
(7),
v
v
v
v
v
6
(8)
(1)
(4)
Stratix II Device Handbook, Volume 1
Down to 125-ps increments (3),
m/(n × post-scale counter)
Fast PLL
Stratix II Architecture
v
v
v
v
(6)
4
(5)
(2)
2–59
(4)