EP2S60F672I4N Altera, EP2S60F672I4N Datasheet - Page 63
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672I4N
Manufacturer Part Number
EP2S60F672I4N
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672I4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1916
EP2S60F672I4N
EP2S60F672I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA
Quantity:
400
Part Number:
EP2S60F672I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 63 of 238
- Download datasheet (3Mb)
Altera Corporation
May 2007
Figure 2–38. Regional Clock Control Blocks
Notes to
(1)
(2)
(3)
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select
blocks.The clock outputs from corner PLLs cannot be dynamically selected
through the global clock control block.
The clock outputs from corner PLLs cannot be dynamically selected through the
global clock control block.
Figure
PLL Counter
2–38:
Outputs
(3)
2
CLKp
Pin
Enable/
Disable
RCLK
CLKn
Pin
Stratix II Device Handbook, Volume 1
(2)
Internal
Logic
Static Clock Select (1)
Internal
Logic
Stratix II Architecture
2–55
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