XC5VSX35T-1FFG665C Xilinx Inc, XC5VSX35T-1FFG665C Datasheet - Page 154
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XC5VSX35T-1FFG665C
Manufacturer Part Number
XC5VSX35T-1FFG665C
Description
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FFG665C
Total Ram Bits
3096576
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
No. Of Logic Blocks
5440
No. Of Gates
35000
Family Type
Virtex-5 SXT
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1566
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Chapter 4: Block RAM
154
Case 3: Reading From a Full FIFO
Prior to the operations performed in
X-Ref Target - Figure 4-23
Clock Event 1 and Clock Event 2: Read Operation and Deassertion of Full Signal
During a read operation on a full FIFO, the content of the FIFO at the first address is
asserted at the DO output pins of the FIFO. Two RDEN operations ensure that the FIFO is
no longer full, and after three WRCLK cycles the FULL pin is deasserted.
The example in
are with respect to read-clock. Clock event 4 appears three write-clock cycles after clock
event 2.
•
•
•
If the rising RDCLK edge is close to the rising WRCLK edge, FULL could be deasserted one
WRCLK period later.
Clock Event 3 and Clock Event 5: Read Operation and Deassertion of Almost
FULL Signal
Three write-clock cycles after the fourth data is read from the FIFO, the Almost FULL pin
is deasserted to signify that the FIFO is not in the almost FULL state.
The example in
respect to read-clock, while clock event 5 is with respect to write-clock. Clock event 5
appears three write-clock cycles after clock event 3.
•
•
WRCLK
RDCLK
WREN
AFULL
RDEN
FULL
At time T
RDEN input of the FIFO.
At time T
outputs of the FIFO.
At time T
Read enable remains asserted at the RDEN input of the FIFO.
At time T
AFULL pin.
DO
FCCK_RDEN
FCKO_DO
FCKO_FULL
FCKO_AFULL
1
Figure 4-23
Figure 4-23
T
FCCK_RDEN
00
, after clock event 1 (RDCLK), data 00 becomes valid at the DO
T
2
Figure 4-23: Reading From a Full FIFO
, after clock event 4 (WRCLK), FULL is deasserted.
FCKO_DO
, before clock event 1 (RDCLK), read enable becomes valid at the
, after clock event 5 (RDCLK), Almost FULL is deasserted at the
www.xilinx.com
reflects both standard and FWFT modes. Clock event 3 is with
reflects both standard and FWFT modes. Clock event 1 and 2
01
Figure
02
3
4-23, the FIFO is completely full.
4
03
T
FCKO_FULL
04
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
5
05
T
ug190_4_19_040606
FCKO_AFULL
06
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