XC5VSX35T-1FFG665C Xilinx Inc, XC5VSX35T-1FFG665C Datasheet - Page 317
![IC FPGA VIRTEX-5 35K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX35T-1FFG665C
Manufacturer Part Number
XC5VSX35T-1FFG665C
Description
IC FPGA VIRTEX-5 35K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX35T-1FFG665C
Total Ram Bits
3096576
Number Of Logic Elements/cells
34816
Number Of Labs/clbs
2720
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
No. Of Logic Blocks
5440
No. Of Gates
35000
Family Type
Virtex-5 SXT
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1566
Available stocks
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SelectIO Logic Resources
Introduction
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
This chapter describes the logic directly behind the I/O drivers and receivers covered in
Chapter 6, SelectIO
Virtex-5 FPGAs contain all of the basic I/O logic resources from Virtex-II/Virtex-II Pro
FPGAs. These resources include the following:
•
•
•
•
•
•
In addition, Virtex-5 FPGAs implement the following architectural features that are also
supported in Virtex-4 FPGAs:
•
•
•
Combinatorial input/output
3-state output control
Registered input/output
Registered 3-state output control
Double-Data-Rate (DDR) input/output
DDR output 3-state control
IODELAY provides users control of an adjustable, fine-resolution delay element
SAME_EDGE output DDR mode
SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode
Resources.
www.xilinx.com
Chapter 7
317
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