EPF10K30AQC240-3N Altera, EPF10K30AQC240-3N Datasheet - Page 59
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EPF10K30AQC240-3N
Manufacturer Part Number
EPF10K30AQC240-3N
Description
IC FLEX 10KA FPGA 30K 240-PQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30AQC240-3N
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
189
Number Of Gates
69000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KA
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
189
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1941
EPF10K30AQC240-3N
EPF10K30AQC240-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K30AQC240-3N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
LUT
CLUT
RLUT
PACKED
EN
CICO
CGEN
CGENR
CASC
C
CO
COMB
Table 32. LE Timing Microparameters (Part 1 of 2)
Symbol
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 32
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis.
timing parameters.
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Dedicated
Clock
through
Parameter
36
describe the FLEX 10K device internal timing
Tables 37
Note (1)
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
through
Q
Q
Q
38
describe FLEX 10K external
t
OUTCOBIDIR
t
t
XZBIDIR
ZXBIDIR
t
t
INHBIDIR
INSUBIDIR
Bidirectional
Pin
Conditions
59