EPF10K30AQC240-3N Altera, EPF10K30AQC240-3N Datasheet - Page 61
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EPF10K30AQC240-3N
Manufacturer Part Number
EPF10K30AQC240-3N
Description
IC FLEX 10KA FPGA 30K 240-PQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30AQC240-3N
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
189
Number Of Gates
69000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KA
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
189
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1941
EPF10K30AQC240-3N
EPF10K30AQC240-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K30AQC240-3N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
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EABDATA1
EABDATA2
EABWE1
EABWE2
EABCLK
EABCO
EABBYPASS
EABSU
EABH
AA
WP
WDSU
WDH
WASU
WAH
WO
DD
EABOUT
EABCH
EABCL
Table 34. EAB Timing Microparameters
Symbol
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
EAB register clock delay
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
Address access delay
Write pulse width
Data setup time before falling edge of write pulse
Data hold time after falling edge of write pulse
Address setup time before rising edge of write pulse
Address hold time after falling edge of write pulse
Write enable to data output valid delay
Data-in to data-out valid delay
Data-out delay
Clock high time
Clock low time
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Note (1)
Parameter
(5)
(5)
(5)
(5)
Conditions
61