EPF10K30AQC240-3N Altera, EPF10K30AQC240-3N Datasheet - Page 63
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EPF10K30AQC240-3N
Manufacturer Part Number
EPF10K30AQC240-3N
Description
IC FLEX 10KA FPGA 30K 240-PQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30AQC240-3N
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
189
Number Of Gates
69000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KA
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
189
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1941
EPF10K30AQC240-3N
EPF10K30AQC240-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K30AQC240-3N
Manufacturer:
ALTERA
Quantity:
20 000
Altera Corporation
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t
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t
DIN2IOE
DCLK2LE
DIN2DATA
DCLK2IOE
DIN2LE
SAMELAB
SAMEROW
SAMECOLUMN
DIFFROW
TWOROWS
LEPERIPH
LABCARRY
LABCASC
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Table 38. External Bidirectional Timing Parameters
Table 36. Interconnect Timing Microparameters
Table 37. External Timing Parameters
DRR
INSU
INH
OUTCO
Symbol
Symbol
Symbol
Setup time for bidirectional pins with global clock at adjacent LE register
Hold time for bidirectional pins with global clock at adjacent LE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
Delay from dedicated input pin to IOE control input
Delay from dedicated clock pin to LE or EAB clock
Delay from dedicated input or clock to LE or EAB data
Delay from dedicated clock pin to IOE clock
Delay from dedicated input pin to LE or EAB control input
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
Routing delay for an LE driving an IOE in the same column
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Notes
Parameter
Parameter
Parameter
(8),
(10)
Note (1)
Note (10)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(9)
Conditions
Conditions
Condition
63