EP1S20F672C7 Altera, EP1S20F672C7 Datasheet - Page 76

• Manufacturer Part Number: EP1S20F672C7
• Description: IC STRATIX FPGA 20K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F672C7

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 426
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1113

Digital Signal Processing Block
Figure 2–34. Adder/Output Blocks
Notes to
(1)
(2)
2–62
Stratix Device Handbook, Volume 1
accum_sload0 (2)
accum_sload1 (2)
Adder/output block shown in
blocks and two summation blocks.
These signals are either not registered, registered once, or registered twice to match the data path pipeline.
addnsub1 (2)
addnsub3 (2)
Figure
signa (2)
signb (2)
Result C
Result D
Result A
Result B
2–34:
Figure 2–34
Accumulator1
Accumulator2
Subtractor/
Subtractor/
Note (1)
Adder/
Adder/
is in 18
×
Summation
18-bit mode. In 9 × 9-bit mode, there are four adder/subtractor
Accumulator Feedback
Accumulator Feedback
Altera Corporation
overflow0
overflow1
Output Selection
Multiplexer
Output
Register Block
July 2005