EP1S25F780C7N Altera, EP1S25F780C7N Datasheet - Page 203

• Manufacturer Part Number: EP1S25F780C7N
• Description: IC STRATIX FPGA 25K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S25F780C7N

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 597
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 597
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1860; EP1S25F780C7N

Altera Corporation
January 2006
External Timing Parameters
External timing parameters are specified by device density and speed
grade.
IOE pin timing. All registers are within the IOE.
Figure 4–4. External Timing in Stratix Devices
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
24-mA current strength and fast slew rate. For external I/O timing using
standards other than LVTTL or for different current strengths, use the I/O
standard input and output delay adders in
Dedicated
Clock
Figure 4–4
shows the pin-to-pin timing model for bidirectional
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
Q
Q
Q
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
Tables 4–103
Bidirectional
Pin
through 4–108.
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
4–33