EP1S25F780C5 Altera, EP1S25F780C5 Datasheet - Page 119
EP1S25F780C5
Manufacturer Part Number
EP1S25F780C5
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C5
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1120
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Figure 2–59. Stratix IOE Structure
Altera Corporation
July 2005
Logic Array
Output B
Output A
Input B
Input A
OE
Output Register
Output Register
The IOEs are located in I/O blocks around the periphery of the Stratix
device. There are up to four IOEs per row I/O block and six IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–60
Figure 2–61
D
D
Q
Q
shows how a row I/O block connects to the logic array.
shows how a column I/O block connects to the logic array.
CLK
OE Register
OE Register
D
D
Q
Q
Input Register
Input Register
Stratix Device Handbook, Volume 1
D
D
Q
Q
Input Latch
D
ENA
Stratix Architecture
Q
2–105