EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 103
EP2SGX60EF1152C3N
Manufacturer Part Number
EP2SGX60EF1152C3N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C3N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2181
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C3N
Manufacturer:
ATMEL
Quantity:
1 420
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Figure 2–67. Global Clock Control Blocks
Notes to
(1)
(2)
Figure 2–68. Regional Clock Control Blocks
Notes to
(1)
(2)
Altera Corporation
October 2007
These clock select signals can be dynamically controlled through internal logic when the device is operating in user
mode.
These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object
File [.pof]) and cannot be dynamically controlled during user mode operation.
These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Figure
Figure
2–67:
2–68:
CLKSELECT[1..0]
(1)
This multiplexer supports
User-Controllable
Dynamic Switching
Figures 2–67
clock, regional clock, and PLL external clock output, respectively.
PLL Counter
PLL Counter
Outputs
Outputs
2
2
through
2
CLKp
CLKp
Pins
Pin
Enable/
Disable
RCLK
2
CLKn
Pin
2–69
Enable/
Disable
GCLK
CLKn
Pin
(2)
Internal
show the clock control block for the global
Logic
Static Clock Select (1)
Internal
Logic
Internal
Logic
Internal
Static Clock Select
Logic
Stratix II GX Device Handbook, Volume 1
(2)
Stratix II GX Architecture
2–95
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