EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 269
EP2SGX60EF1152C3N
Manufacturer Part Number
EP2SGX60EF1152C3N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C3N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2181
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C3N
Manufacturer:
ATMEL
Quantity:
1 420
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LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class I I
1.5-V HSTL Class I
1.5-V HSTL Class I I
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Differential SSTL-18
Class I
PCI
PCI-X
Table 4–88. Stratix II GX Maximum Input Clock Rate for Column I/O Pins (Part 1 of 2)
I/O Standard
-3 Speed Grade
To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
Table 4–88
device column pins.
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
shows the maximum input clock toggle rates for Stratix II GX
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
-5 Speed Grade
450
450
450
450
450
500
500
500
500
500
500
500
500
450
450
500
500
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
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