EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 98
EP2SGX60EF1152C3N
Manufacturer Part Number
EP2SGX60EF1152C3N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C3N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2181
Available stocks
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Quantity
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EP2SGX60EF1152C3N
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ATMEL
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1 420
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PLLs and Clock Networks
Figure 2–61. Global Clocking
2–90
Stratix II GX Device Handbook, Volume 1
CLK[3..0]
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout.
pins driving global clock networks.
Regional Clock Network
There are eight regional clock networks (RCLK[7..0]) in each quadrant
of the Stratix II GX device that are driven by the dedicated
CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal
logic. The regional clock networks provide the lowest clock delay and
skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as
shown in
Figure
Global Clock [15..0]
2–62.
CLK[7..4]
CLK[15..12]
Figure 2–61
Global Clock [15..0]
shows the 12 dedicated CLK
Altera Corporation
October 2007
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