XC3S700AN-4FGG484I Xilinx Inc, XC3S700AN-4FGG484I Datasheet - Page 42
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XC3S700AN-4FGG484I
Manufacturer Part Number
XC3S700AN-4FGG484I
Description
IC FPGA SPARTAN -3AN700K 484FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-4FGG484I
Total Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
No. Of Logic Blocks
1472
No. Of Gates
700000
No. Of Macrocells
13248
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
372
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1598
XC3S700AN-4FGG484I
XC3S700AN-4FGG484I
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-4FGG484I
Manufacturer:
XILINX
Quantity:
325
Company:
Part Number:
XC3S700AN-4FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 30: Test Methods for Timing Measurement at I/Os (Cont’d)
The capacitive load (C
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
Differential
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
L
value of zero. High-impedance probes (less than 1 pF)
Descriptions of the relevant symbols are as follows:
V
V
V
V
V
R
V
The load capacitance (C
According to the PCI specification. For information on PCI IP solutions, see
www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
REF
ICM
M
L
H
T
Signal Standard
T
(IOSTANDARD)
– Low-level test voltage at Input pin
– Effective termination resistance, which takes on a value of 1 M when no parallel termination is required
– Termination voltage
– High-level test voltage at Input pin
– Voltage of measurement point on signal transition
– The common mode input voltage
– The reference voltage for setting the input switching threshold
L
) is connected between the output
L
) at the Output pin is 0 pF for all signal standards.
V
REF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(V)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
V
Inputs
L
– 0.125
– 0.125
– 0.125
– 0.125
– 0.125
(V)
– 0.3
– 0.3
– 0.1
– 0.1
– 0.1
– 0.1
– 0.1
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
V
H
+ 0.125
+ 0.125
+ 0.125
+ 0.125
+ 0.125
(V)
+ 0.3
+ 0.3
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
R
N/A
N/A
T
1M
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
()
Outputs
(2)
V
0.75
1.25
1.25
N/A
N/A
T
1.2
1.2
1.2
1.2
1.2
1.2
3.3
0.8
0.8
1.5
0.9
0.9
1.8
0.9
0.9
1.5
1.5
0
(V)
Inputs and
Outputs
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
M
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
ICM
(V)
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