XC3S700AN-4FGG484I Xilinx Inc, XC3S700AN-4FGG484I Datasheet - Page 91
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XC3S700AN-4FGG484I
Manufacturer Part Number
XC3S700AN-4FGG484I
Description
IC FPGA SPARTAN -3AN700K 484FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-4FGG484I
Total Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
No. Of Logic Blocks
1472
No. Of Gates
700000
No. Of Macrocells
13248
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
372
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1528 - KIT STARTER SPARTAN-3 AN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1598
XC3S700AN-4FGG484I
XC3S700AN-4FGG484I
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-4FGG484I
Manufacturer:
XILINX
Quantity:
325
Company:
Part Number:
XC3S700AN-4FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
FTG256 Footprint (XC3S200AN, XC3S400AN)
X-Ref Target - Figure 21
DS557 (v4.1) April 1, 2011
Product Specification
69
21
2
0
I/O: Unrestricted,
general-purpose user I/O
INPUT: Unrestricted,
general-purpose input pin
CONFIG: Dedicated
configuration pins
N.C.: Not connected
M
A
B
C
D
E
G
H
K
N
P
R
F
J
L
T
VREF_3
LHCLK1
LHCLK5
LHCLK7
VREF_3
L01N_3
L03P_3
L03N_3
L08P_3
L08N_3
L11N_3
L14N_3
L15N_3
L16P_3
L20P_3
L20N_3
L22N_3
L23P_3
GND
GND
Figure 21: XC3S200AN and XC3S400AN FPGA in FTG256 Package Footprint (Top View)
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
VCCO_3
VCCO_3
VCCO_3
LHCLK0
LHCLK4
L05N_3
L16N_3
L23N_3
L02N_2
L01P_3
L11P_3
L14P_3
L22P_3
L02P_2
CSO_B
TMS
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M2
2
RDWR_B
LHCLK2
LHCLK3
LHCLK6
L19P_0
L19N_0
L02N_3
L05P_3
L07P_3
L09P_3
L12P_3
L12N_3
L15P_3
L18N_3
L19P_3
L24P_3
L03P_2
L03N_2
TRDY2
IRDY2
GND
GND
VS2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
51
32
28
VCCO_2
VREF_0
VREF_3
L18N_0
INPUT
INPUT
L07N_3
L09N_3
L19N_3
L24N_3
L01N_2
4
L18P_0
L20P_0
L02P_3
L04P_3
L04N_3
L17P_3
L18P_3
L01P_2
L05P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M0
M1
4
DUAL: Configuration pins,
then possible user I/O
CLK: User I/O, input, or
global buffer input
JTAG: Dedicated JTAG
port pins
GND: Ground
VCCAUX
VCCO_0
PUDC_B
VCCO_3
INPUT
VREF_3
INPUT
INPUT
INPUT
VREF_2
L17P_0
L17N_0
L20N_0
L06N_3
L10N_3
L21P_3
L25P_3
L04N_2
L05N_2
L06P_2
GND
GND
VS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D7
5
VCCAUX
INPUT
INPUT
INPUT
INPUT
INPUT
VREF_3
L15P_0
L15N_0
L16N_0
L06P_3
L10P_3
L17N_3
L21N_3
L25N_3
L04P_2
L07N_2
L06N_2
GND
GND
VS1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D6
6
VCCINT
VREF_0
VREF_2
GCLK12
GCLK13
L13N_0
L14N_0
INPUT
INPUT
INPUT
L13N_3
INPUT
INPUT
L09N_2
L13P_0
L16P_0
L13P_3
L07P_2
L08P_2
L09P_2
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D5
7
www.xilinx.com
Bank 2
VCCINT
VCCINT
GCLK10
GCLK11
VCCO_0
GCLK14
VCCO_2
GCLK15
INPUT
INPUT
VREF_2
L12P_0
L12N_0
L11P_0
L11N_0
L14P_0
L08N_2
L10P_2
L10N_2
GCLK8
GCLK9
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
8
Bank 0
21
16
VCCINT
VCCINT
VCCO_0
VCCO_2
VREF_0
VREF_2
INPUT
INPUT
INPUT
6
4
L10N_0
L10P_0
L09N_0
L11P_2
L11N_2
L12P_2
L12N_2
GCLK7
GCLK6
GCLK5
GCLK0
GCLK1
GCLK2
GCLK3
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
VREF: User I/O or input
voltage reference for bank
VCCO: Output voltage
supply for bank
VCCINT: Internal core
supply voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage
VCCINT
VREF_0
VREF_1
VREF_2
L08N_0
L08P_0
L09P_0
L06P_0
L06N_0
INPUT
INPUT
L13P_1
INPUT
L09P_1
INPUT
L13N_2
L13P_2
L14N_2
L14P_2
GCLK4
CSI_B
GND
MOSI
GND
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Spartan-3AN FPGA Family: Pinout Descriptions
VCCAUX
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF_2
AWAKE
L07N_0
L07P_0
L03N_0
L25N_1
L21N_1
L13N_1
L09N_1
L04P_1
L16N_2
L16P_2
L15N_2
L15P_2
GND
GND
DOUT
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
VCCO_1
VCCO_2
VREF_1
VREF_1
VREF_1
L05N_0
INPUT
INPUT
INPUT
INPUT
L17N_2
L05P_0
L03P_0
L25P_1
L21P_1
L10P_1
L04N_1
L19P_2
L17P_2
INIT_B
GND
GND
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A8
D3
VCCO_0
L04N_0
L01N_0
L01P_0
L23P_1
L20N_1
L19P_1
L17P_1
L10N_1
L06N_1
L06P_1
L05P_1
L01P_1
L19N_2
L18N_2
L18P_2
HDC
A22
A19
A16
A12
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D1
A9
A3
A2
D2
DIN/MISO
RHCLK5
RHCLK4
RHCLK1
VREF_1
2
L04P_0
L02N_0
L23N_1
L20P_1
L19N_1
L17N_1
L14N_1
L14P_1
L11N_1
L08P_1
L05N_1
L01N_1
L20N_2
L20P_2
GND
GND
CCLK
LDC2
A23
A18
A17
A13
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A6
D0
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
VCCO_1
RHCLK6
VCCO_1
RHCLK0
VCCO_1
VREF_0
L24N_1
L22N_1
L18N_1
L02N_1
DONE
L02P_0
L15P_1
L11P_1
L07P_1
L02P_1
IRDY1
TCK
GND
GND
LDC0
LDC1
15
I/O
I/O
A25
I/O
A21
I/O
A15
I/O
I/O
I/O
I/O
I/O
A4
DS529-4_06_012009
RHCLK7
RHCLK3
RHCLK2
L24P_1
L22P_1
L18P_1
L16N_1
L16P_1
L15N_1
L12N_1
L12P_1
L08N_1
L07N_1
L03N_1
L03P_1
TRDY1
GND
GND
TDO
A24
A20
A14
A11
A10
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A7
A5
A1
A0
91