XC4013-6PQ240C Xilinx Inc, XC4013-6PQ240C Datasheet - Page 20

• Manufacturer Part Number: XC4013-6PQ240C
• Description: IC LOGIC CL ARRAY 13K GAT 240PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4013-6PQ240C

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 192
• Number Of Gates: 13000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1074

XC4000, XC4000A, XC4000H Logic Cell Array Families
Figure 19. Internal Configuration Data Structure.
Format
The configuration-data stream begins with a string of ones,
a 0010 preamble code, a 24-bit length count, and a four-
bit separator field of ones. This is followed by the actual
configuration data in frames, each starting with a zero bit
and ending with a four-bit error check. For each XC4XXX
device, the MakeBits software allows a selection of CRC
or non-CRC error checking. The non-CRC error checking
tests for a 0110 end of frame field for each frame of a
selected LCA device. For CRC error checking, MakeBits
software calculates a running CRC of inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an LCA device includes the
Device
Gates
CLBs
(Row x Col)
IOBs
Flip-flops
Horizontal
TBUF Longlines
TBUFs/Longline
Bits per Frame
Frames
Program Data
PROM size (bits)
XC4000, 4000H: Bits per Frame = (10 x number of Rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
XC4000A:
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any
frame, following the four error check bits, but the Length Count value must be adjusted for all such extra "one" bits,
even for leading extra ones at the beginning of the header.
11111111
0010
< 24-BIT LENGTH COUNT >
1111
0 < DATA FRAME # 001 > eeee
0 < DATA FRAME # 002 > eeee
0 < DATA FRAME # 003 > eeee
0 < DATA FRAME # N-1 > eeee
0 < DATA FRAME # N > eeee
0111 1111
XC4002A XC4003A XC4003/H XC4004A XC4005A XC4005/H XC4006
31,628
31,668
(8 x 8)
Number of Frames = (36 x number of Columns) + 26 for the left edge + 41 for the right edge + 1
Bits per Frame = (10 x number of Rows) + 6 for the top + 10 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (32 x number of Columns) + 21 for the left edge + 32 for the right edge + 1
2,000
256
102
310
64
64
16
10
.
.
.
.
(10 x 10)
.
.
.
.
45,636
45,676
3,000
100
360
122
374
80
20
12
.
.
.
.
(10 x 10)
360/300
80/.160
53,936
53,976
3,000
100
126
428
20
12
(12 x 12)
62,204
62,244
4,000
144
480
142
438
96
24
14
– EIGHT DUMMY BITS MINIMUM
– PREAMBLE CODE
– CONFIGURATION PROGRAM LENGTH (MSB FIRST)
– DUMMY BITS (4 BITS MINIMUM)
POSTAMBLE CODE
(14 x 14)
81,332
81,372
5000
196
112
616
162
502
28
16
(EACH FRAME CONSISTS OF:
A START BIT (0)
A DATA FIELD
FOUR ERROR CHECK BITS (eeee)
2-26
112 (192)
616 (392)
(14 x 14)
94,960
95,000
5,000
196
166
572
28
16
last seven data bits. Detection of an error results in
suspension of data loading and the pulling down of the INIT
pin. In master modes, CCLK and address signals continue
to operate externally. The user must detect INIT and
initialize a new configuration by pulsing the PROGRAM pin
or cycling V
on the device type. Multiple LCA devices can be con-
nected in a daisy chain by wiring their CCLK pins in parallel
and connecting the DOUT of each to the DIN of the next.
The lead-master LCA device and following slaves each
passes resynchronized configuration data coming from a
single source. The Header data, including the length
count, is passed through and is captured by each LCA
(16 x 16)
119,792
119,832
6,000
256
128
768
186
644
32
18
CC
(18 x 18)
. The length and number of frames depend
147,504
147,544
XC4008 XC4010/D XC4013/D XC4020
8,000
936
324
144
206
716
36
20
(20 x 20)
178,096
178,136
10,000
1,120
160
400
226
788
40
22
HEADER
PROGRAM DATA
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
(24 x 24)
247,920
247,960
13,000
1,536
576
192
266
932
48
26
(28 x 28)
329,264
329,304
20,000
2,016
1,076
784
224
306
56
30
(32 x 32)
XC4025
422,128
422,168
25,000
1,024
2,560
1,220
256
346
64
34
X1526