EP3C16F484C7 Altera, EP3C16F484C7 Datasheet - Page 19

• Manufacturer Part Number: EP3C16F484C7
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2470

Board Design Considerations
Power Consideration
© November 2008 Altera Corporation
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Termination Schemes
Correct termination is important to prevent signal reflection on the signal lines.
Depending on the I/O standards used and the direction of the signals travel, the
termination scheme you should use on the boards may be different. Series and
parallel termination can be used. As a general guideline, series termination is
normally used at the transmitter, while parallel termination is used at the receiver
end. The value of the termination resistors should match the trace impedance. You can
also perform board-level simulation to obtain the suitable resistance values based on
your termination scheme.
The Cyclone III device has on-chip series termination (with and without calibration)
that you can use to replace the series termination resistors on your board.
For information about the various termination schemes, refer to the
I/O Features
Board Layout
Board-Level Simulation
To ensure that the selected I/O signaling meets receiver threshold levels with the
board setup, perform simulation with third-party board-level simulation tools using
the Cyclone III IBIS or HSPICE model. Both the IBIS and HSPICE models describe the
behavior of I/O buffers, but in a different way. The IBIS models describe the I/O
buffers with voltage-current and voltage-time data curves while the HSPICE models
describe the I/O buffers by their physical properties, such as transistor characteristics,
parasitic capacitance and their connections to one another. You can download the IBIS
and HSPICE models from
the Quartus II software to create custom IBIS and HSPICE models for your design and
perform simulation with the models to check the effect of the termination scheme on
your board signals.
For information about performing simulation with IBIS and HSPICE models, refer to
the
Handbook.
Table 7
Table 7. Cyclone III Power Supply Requirements
For the possible values of each power supply and the recommendation operation
conditions, refer to the
chapter in volume 2 of the Cyclone III Device Handbook.
V
V
V
V
V
C C I N T
C C I O
C C A
C C D _ PL L
R E F
Signal Integrity Analysis with Third-Party Tools
Power Supply
describes the external power supplies needed to power Cyclone III devices.
chapter in volume 1 of the Cyclone III Device Handbook,
Guidelines, and
Core voltage power supply
I/O power supply to the input and output buffers in Bank 1 to Bank 8.
Analog power supply for PLL.
Digital power supply for PLL.
Input reference voltage for voltage-reference I/O standards.
Cyclone III Device Datasheet: DC and Switching Characteristics
www.altera.com
AN 315: Guidelines for Designing High-Speed FPGA PCBs.
when they are available. You can also use
Description
chapter in volume 3 of the Quartus II
AN 224: High-Speed
Cyclone III Device
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