EP3C16F484C7 Altera, EP3C16F484C7 Datasheet - Page 55

• Manufacturer Part Number: EP3C16F484C7
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2470

Design Debugging
Design Debugging
© November 2008 Altera Corporation
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You can perform simulation on your Cyclone III design using various simulation
tools. Among the commonly used third-party simulation tools are the Mentor
Graphics ModelSim
ModelSim-Altera edition, ModelSim-Altera web edition as well as the Quartus II
Simulator. Both ModelSim-Altera edition and ModelSim-Altera web edition support
the Cyclone III family.
These third-party simulation tools support functional RTL, post-synthesis and
gate-level simulation. Perform functional RTL simulation before gate-level simulation
or post-synthesis simulation as functional RTL simulation verifies the functionality of
your design before synthesis and place-and-route.
Post-synthesis simulation verifies the functionality of a design after synthesis has
been performed. You can create a post-synthesis netlist in the Quartus II software and
use this netlist to perform post-synthesis simulation with the third-party simulation
tools. After the post-synthesis version of the design is verified, you can then proceed
with the place-and-route for your design in the target Cyclone III device using the
Quartus II Fitter. Use the EDA Netlist Writer of the Quartus II software to generate the
simulation netlist for the specific third-party simulation tool.
Gate-level timing simulation is a post place-and-route simulation to verify the
operation of the design after the worst-case timing delays have been calculated.
Similarly, the Quartus II Simulator supports both functional and timing simulation.
Perform functional simulation at the beginning of your design flow to check the
functionality or logical behavior of your design. You do not need to compile your
design, simply generate the functional simulation netlist of your design which does
not contain timing information to perform functional simulation.
Timing simulation uses the timing netlist generated by the Timing Analyzer when
you compile your design. Timing simulation takes the delay of different device blocks
as well as place-and-route information into consideration, thus is more accurate than
the functional simulation. Perform timing simulation at the top-level design, at the
end of your design flow to ensure that your design works in the targeted device.
For more information about simulating your design with simulation tools, refer to
Simulation
Using incremental compilation when performing on-chip debugging reduces the
compilation time as changes are usually made only to certain parts of the design.
For more information on the on-chip debugging features available in the Quartus II
software, refer to the
Planning” on page
section in volume 3 of the Quartus II Handbook.
3.
®
“Planning for On-Chip Debugging”
, Synopsys VCS and Cadence NC-Sim. You can also use the
section under
“Early System
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