EP3C16F484C7 Altera, EP3C16F484C7 Datasheet - Page 4

• Manufacturer Part Number: EP3C16F484C7
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2470

Page 4
Early Power Estimation
I/O Support
Table 3. Selection Criteria for Each I/O Signaling Type (Part 1 of 2)
Single-ended
Voltage-referenced
(single-ended and
differential)
I/O Signaling Type
(1)
f
As FPGAs have increased in logic capacity and performance, the power consumption
must be accurately estimated for appropriate power supply, decoupling and thermal
solution planning. The power supply must be able to provide enough current for the
device operation and the thermal solution must be able to cool the device junction
temperature to within the specification. Altera provides a power estimation tool
called the Early Power Estimator (EPE) to help you estimate the power consumption
of your design during the system planning phase. The EPE allows you to estimate the
power consumption, current drawn from the power supply and device junction
temperature based on the device resources that you are going to use in your design,
along with the information about the ambient temperature, heat sink, air flow and
board thermal model.
You can either enter the design information manually into the spreadsheet or import a
power estimator file of a fully or partially completed design from the Quartus II
software. After importing a file, you can edit some of the input parameters such as the
ambient temperature, airflow, clock frequency and toggle percentage to suit your
system requirements.
For more information about the EPE and ways generate and import the power
estimator file, refer to the
FPGAs.
This section discusses the general Cyclone III device I/O support. Before starting with
the I/O planning, take some time to review the support offered by the Cyclone III
I/Os.
Selectable I/O Standards
Cyclone III devices support a wide range of industry I/O standards, including
single-ended, voltage-referenced and differential I/O standards. Selection factors are
driven by performance versus cost.
signaling type.
Slow speed rail-to-rail interface, limited by large voltage
swing and noise.
Reduced Simultaneous Switching Output (SSO) effects
from large number of pins changing levels at the same
time. Improved logic transition rate with reduced
voltage swing and minimized noise caused by
reflections due to termination requirements of the I/O
standard.
Performance
PowerPlay Early Power Estimator User Guide for Cyclone III
Selection Criteria
Table 3
simplifies the selection choice for each I/O
Fairly low, unless reflection causes signal
integrity concerns, whereby termination
is required.
High, with extra components due to
termination requirement and additional
clean reference voltage, V
© November 2008 Altera Corporation
Cost
Early System Planning
TT
.