EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet

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... Up to 360 18 × 18 multipliers for DSP processing intensive applications ■ Protocol bridging applications for under 1.5 W total power ■ © March 2010 Altera Corporation 1. Cyclone IV FPGA Device Family ® IV FPGA device family extends the Cyclone FPGA series Power Requirements for Cyclone IV chapter ...

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... V-by-One (up to 3.0 Gbps) ■ DisplayPort (2.7 Gbps) ■ Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps) ■ OBSAI (up to 3.072 Gbps) ■ Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Cyclone IV Device Family Features © March 2010 Altera Corporation ...

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... Table 1–1. Resources for the Cyclone IV E Device Family Resources Logic elements (LEs) 6,272 10,320 Embedded memory 270 414 (Kbits) Embedded 18 × multipliers General-purpose 2 PLLs Global Clock 10 Networks User I/O Banks 8 Maximum user I/O 179 179 © March 2010 Altera Corporation 15,408 22,320 28,848 504 594 594 ...

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... Clock Clock Networks and PLLs in Cyclone IV Devices © March 2010 Altera Corporation ...

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Package Matrix Table 1–3 lists Cyclone IV E device package offerings. Table 1–3. Package Offerings for the Cyclone IV E Device Family Package E144 Size (mm) 22 × 22 Pitch (mm) 0.5 Device User I/O LVDS (2) EP4CE6 91 21 ...

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Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts. Table 1–4. Package Offerings for the Cyclone IV GX Device Family Package N148 F169 Size (mm) 11 × × 14 Pitch (mm) 0.5 LVDS ...

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... EP4CE75 EP4CE115 Notes to Table 1–6 (1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage. (2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage. © March 2010 Altera Corporation F169 F324 F484 — — C6, C7, C8, I7 — ...

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... The multiplier architecture in Cyclone IV devices is the same as in the existing Cyclone series devices. The embedded multiplier blocks can implement an 18 × two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP including finite impulse response (FIR), fast Fourier transform (FFT), and numerically controlled oscillator (NCO) functions for use with the multiplier blocks ...

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... Interfaces may span two or more sides of the device to allow more flexible board design. The Altera interface solution consists of a PHY interface and a memory controller. Altera supplies the PHY IP and you can use it in conjunction with your own custom memory controller or an Altera-provided memory controller ...

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... Cyclone IV devices use SRAM cells to store configuration data. Configuration data is downloaded to the Cyclone IV device each time the device powers up. Low-cost configuration options include the Altera EPCS family serial flash devices and commodity parallel flash configuration options. These options provide the flexibility for general-purpose applications and the ability to meet specific configuration and wake-up time requirements of the applications ...

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... You can configure the block with the Quartus II software’s PCI Express Compiler, which guides you through the process step by step. f For more information, refer to the © March 2010 Altera Corporation Transmitter Channel PCS TX Phase Compensation Byte Serializer ...

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... Reference and Ordering Information Optional Suffix Indicates specific device shipment method ES: Engineering sample N: Lead-free devices Speed Grade with 6 being the fastest = 0° 85° -40° 100° C) © March 2010 Altera Corporation ...

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... Chapter Revision History Table 1–10 lists the revision history for this chapter. Table 1–10. Chapter Revision History Date Version March 2010 1.2 February 2010 1.1 November 2009 1.0 © March 2010 Altera Corporation EP4CE Package 17 = 256 pins 22 = 144 pins 23 = 484 pins 29 = 780 pins ...

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... Cyclone IV Device Handbook, Volume 1 Chapter 1: Cyclone IV FPGA Device Family Overview Chapter Revision History © March 2010 Altera Corporation ...