EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 9

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Architecture
I/O Features
Clock Management
External Memory Interfaces
© March 2010 Altera Corporation
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Cyclone IV device I/O supports programmable bus hold, programmable pull-up
resistors, programmable delay, programmable drive strength, programmable
slew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices
support calibrated on-chip series termination (Rs OCT) or driver impedance matching
(Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speed
transceiver I/Os are located on the left side of the device. The top, bottom, and right
sides can implement general-purpose user I/Os.
Table 1–8
Table 1–8. I/O Standards Support for the Cyclone IV Device Family
The LVDS SERDES is implemented in the core of the device using logic elements.
For more information, refer to the
Cyclone IV devices include up to 30 global clock (GCLK) networks and up to eight
PLLs with five outputs per PLL to provide robust clock management and synthesis.
You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the
clock frequency or phase.
Cyclone IV GX devices support two types of PLLs: multi-purpose PLLs (MPLLs) and
general-purpose PLLs (GPLLs):
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For more information, refer to the
chapter.
Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces
on the top, bottom, and right sides of the device. Cyclone IV E devices also support
these interfaces on the left side of the device. Interfaces may span two or more sides of
the device to allow more flexible board design. The Altera
interface solution consists of a PHY interface and a memory controller. Altera supplies
the PHY IP and you can use it in conjunction with your own custom memory
controller or an Altera-provided memory controller. Cyclone IV devices support the
use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces.
For more information, refer to the
chapter.
Single-Ended I/O
Differential I/O
Use MPLLs for clocking the transceiver blocks. You can also use them for
general-purpose clocking when they are not used for transceiver clocking.
Use GPLLs for general-purpose applications in the fabric and periphery, such as
external memory interfaces. Some of the GPLLs can support transceiver clocking.
Type
lists the I/O standards that Cyclone IV devices support.
LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X
SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
I/O Features in Cyclone IV Devices
Clock Networks and PLLs in Cyclone IV Devices
External Memory Interfaces in Cyclone IV Devices
I/O Standard
Cyclone IV Device Handbook, Volume 1
®
DDR SDRAM memory
chapter.
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