EP4CE55F23C8N Altera, EP4CE55F23C8N Datasheet - Page 4

• Manufacturer Part Number: EP4CE55F23C8N
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 324
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–4
Table 1–2. Resources for the Cyclone IV GX Device Family
Cyclone IV Device Handbook, Volume 1
Logic elements (LEs)
Embedded memory (Kbits)
Embedded 18 × 18 multipliers
General-purpose PLLs (GPLLs)
Multi-purpose PLLs (MPLLs)
Global clock networks
High-speed transceivers
Transceiver maximum data rate
(Gbps)
PCIe (PIPE) hard IP blocks
User I/O banks
Maximum user I/O
Notes to
(1) Applicable for the F169 and F324 packages.
(2) Applicable for the F484 package.
(3) You can use the MPLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer to the
(4) Two of the GPLLs are able to support transceiver clocking. For more information, refer to the
(5) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.
(6) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.
(7) If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.
Networks and PLLs in Cyclone IV Devices
chapter.
Table
Resources
1–2:
Table 1–2
(7)
lists Cyclone IV GX device resources.
14,400
2
9
540
2.5
20
72
0
1
2
1
(3)
(5)
chapter.
21,280
2
9
756
150
2.5
40
20
2
4
1
(3)
(5)
29,440
1,080
2
9
150
2.5
20
80
2
(3)
4
1
(5)
29,440
11
1,080
3.125
4
2
290
80
30
(4)
(3)
4
1
(6)
Chapter 1: Cyclone IV FPGA Device Family Overview
49,888
11
2,502
3.125
4
4
Clock Networks and PLLs in Cyclone IV Devices
140
310
30
8
1
(4)
(3)
(6)
73,920
11
4,158
3.125
© March 2010 Altera Corporation
4
4
198
310
30
8
1
(4)
(3)
(6)
109,424
11
5,490
3.125
4
4
280
475
30
8
1
(4)
(3)
(6)
Device Resources
149,760
11
6,480
3.125
4
4
475
360
30
(4)
(3)
8
1
Clock
(6)