EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 113
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EP20K100EFC324-2
Manufacturer Part Number
EP20K100EFC324-2
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100EFC324-2
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
18
Company:
Part Number:
EP20K100EFC324-2
Manufacturer:
PANASONIC
Quantity:
86
Company:
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
25
Company:
Part Number:
EP20K100EFC324-2-3
Manufacturer:
VISHAY
Quantity:
15 000
Company:
Part Number:
EP20K100EFC324-2X
Manufacturer:
ALTERA
Quantity:
15
Altera Corporation
Power
Consumption
Configuration &
Operation
LVCMOS
LVTTL
2.5 V
1.8 V
PCI
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
CTT
AGP
Table 110. Selectable I/O Standard Output Delays
Symbol
Min
-1 Speed Grade
To estimate device power consumption, use the interactive power
calculator on the Altera web site at http://www.altera.com.
The APEX 20K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The APEX architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device operation
is called user mode.
Before and during device configuration, all I/O pins are pulled to V
by a built-in weak pull-up resistor.
–0.03
–0.48
Max
0.00
0.00
0.00
2.49
0.75
1.39
1.11
1.35
1.00
0.00
0.00
APEX 20K Programmable Logic Device Family Data Sheet
Min
-2 Speed Grade
–0.48
Max
0.00
0.00
0.09
2.98
0.17
0.75
1.51
1.23
1.48
1.12
0.00
0.00
Min
-3 Speed Grade
–0.48
Max
0.00
0.00
0.10
3.03
0.16
0.76
1.50
1.23
1.47
1.12
0.00
0.00
Unit
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCIO
113