EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 76

IC APEX 20KE FPGA 100K 324-FBGA

EP20K100EFC324-2

Manufacturer Part Number
EP20K100EFC324-2
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K100EFC324-2

Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
18
Part Number:
EP20K100EFC324-2
Manufacturer:
PANASONIC
Quantity:
86
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
25
Part Number:
EP20K100EFC324-2
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
1 000
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
0
Part Number:
EP20K100EFC324-2-3
Manufacturer:
VISHAY
Quantity:
15 000
Part Number:
EP20K100EFC324-2N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP20K100EFC324-2N
Manufacturer:
ALTERA
0
Part Number:
EP20K100EFC324-2N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP20K100EFC324-2X
Manufacturer:
ALTERA
Quantity:
15
Part Number:
EP20K100EFC324-2X
Manufacturer:
ALTERA
Quantity:
500
APEX 20K Programmable Logic Device Family Data Sheet
Note to
(1)
76
t
t
t
t
t
t
t
t
t
t
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
INSUBIDIRPLL
INHBIDIRPLL
OUTCOBIDIRPLL
XZBIDIRPLL
ZXBIDIRPLL
Table 39. APEX 20KE External Bidirectional Timing Parameters
These timing parameters are sample-tested only.
Symbol
Tables 38
and 39:
Setup time for bidirectional pins with global clock at LAB adjacent Input
Register
Hold time for bidirectional pins with global clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with global clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay
Synchronous Output Enable Register output buffer enable delay
Setup time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Hold time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with PLL clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay with
PLL
Synchronous Output Enable Register output buffer enable delay with PLL
Parameter
Note (1)
Altera Corporation
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
Conditions

Related parts for EP20K100EFC324-2