EPF10K50EQC240-3N Altera, EPF10K50EQC240-3N Datasheet - Page 2

• Manufacturer Part Number: EPF10K50EQC240-3N
• Description: IC FLEX 10KE FPGA 50K 240-PQFP
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K50EQC240-3N

• Number Of Logic Elements/cells: 2880
• Number Of Labs/clbs: 360
• Total Ram Bits: 40960
• Number Of I /o: 189
• Number Of Gates: 199000
• Voltage - Supply: 2.3 V ~ 2.7 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-MQFP, 240-PQFP
• Family Name: FLEX 10KE
• Number Of Usable Gates: 50000
• Number Of Logic Blocks/elements: 2880
• # Registers: 189
• # I/os (max): 189
• Frequency (max): 166.67MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 2880
• Ram Bits: 40960
• Device System Gates: 199000
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 2.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Note to tables:
(1)
(2)
...and More
Features
2
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Table 2. FLEX 10KE Device Features
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
New EPF10K100B designs should use EPF10K100E devices.
(1)
Feature
–
–
–
–
–
–
Flexible interconnect
–
–
–
–
–
Powerful I/O pins
–
–
–
–
–
Fabricated on an advanced process and operate with a 2.5-V
internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
ClockLock
delay/skew and clock multiplication
Built-in low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
Pull-up on I/O pins before and during configuration
FastTrack
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
Clamp to V
Supports hot-socketing
EPF10K100E
®
TM
Interconnect continuous routing structure for fast,
CCIO
100,000
257,000
49,152
4,992
and ClockBoost
338
12
user-selectable on a pin-by-pin basis
(2)
TM
EPF10K130E
130,000
342,000
options for reduced clock
65,536
6,656
413
16
Altera Corporation
EPF10K200E
EPF10K200S
200,000
513,000
98,304
9,984
470
24