EPF10K50EQC240-3N Altera, EPF10K50EQC240-3N Datasheet - Page 60
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EPF10K50EQC240-3N
Manufacturer Part Number
EPF10K50EQC240-3N
Description
IC FLEX 10KE FPGA 50K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K50EQC240-3N
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
189
Number Of Gates
199000
Voltage - Supply
2.3 V ~ 2.7 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
50000
Number Of Logic Blocks/elements
2880
# Registers
189
# I/os (max)
189
Frequency (max)
166.67MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
2880
Ram Bits
40960
Device System Gates
199000
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K50EQC240-3N
Manufacturer:
ALTERA
Quantity:
20 000
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
60
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DIN2IOE
DIN2LE
DCLK2IOE
DCLK2LE
DIN2DATA
SAMELAB
SAMEROW
SAMECOLUMN
DIFFROW
TWOROWS
LEPERIPH
LABCARRY
LABCASC
DRR
INSU
INH
OUTCO
PCISU
PCIH
PCICO
Table 28. Interconnect Timing Microparameters
Table 29. External Timing Parameters
Symbol
Symbol
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated clock pin to IOE clock
Delay from dedicated clock pin to LE or EAB clock
Delay from dedicated input or clock to LE or EAB data
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
Routing delay for an LE driving an IOE in the same column
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
Parameter
Parameter
Note (1)
Altera Corporation
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(7)
(8)
(9)
(9)
(9)
(9)
(9),(10)
(9)
,
,
Conditions
Conditions
(10)
(10)