EP20K100EQC208-1 Altera, EP20K100EQC208-1 Datasheet - Page 42

• Manufacturer Part Number: EP20K100EQC208-1
• Description: IC APEX 20KE FPGA 100K 208-PQFP
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EQC208-1

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 151
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APEX 20K Programmable Logic Device Family Data Sheet
42
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect.
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
Row Interconnect
LAB
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
Figure 27
shows how a row IOE connects to the
MegaLAB Interconnect
IOE
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
Altera Corporation