EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 113
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Quantity
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Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
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Chapter 6: I/O Features in Cyclone IV Devices
I/O Element Features
© December 2010 Altera Corporation
f
Table 6–1
Table 6–1. Cyclone IV Devices Programmable Delay Chain
There are two paths in the IOE for an input to reach the logic array. Each of the two
paths can have a different delay. This allows you to adjust delays from the pin to the
internal logic element (LE) registers that reside in two different areas of the device.
You must set the two combinational input delays with the input delay from pin to
internal cells logic option in the Quartus II software for each path. If the pin uses the
input register, one of the delays is disregarded and the delay is set with the input
delay from pin to input register logic option in the Quartus II software.
The IOE registers in each I/O block share the same source for the preset or clear
features. You can program preset or clear for each individual IOE, but you cannot use
both features simultaneously. You can also program the registers to power-up high or
low after configuration is complete. If programmed to power-up low, an
asynchronous clear can control the registers. If programmed to power-up high, an
asynchronous preset can control the registers. This feature prevents the inadvertent
activation of the active-low input of another device upon power-up. If one register in
an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if
they require preset or clear. Additionally, a synchronous reset signal is available for
the IOE registers.
For more information about the input and output pin delay settings, refer to the
and Timing Optimization
Input pin-to-logic array delay
Input pin-to-input register delay
Output pin
Dual-purpose clock input pin
delay
Note to
(1) Cyclone IV E devices do not support delay from output register to output pin.
Programmable Delay
Table
shows the programmable delays for Cyclone IV devices.
delay(1)
6–1:
chapter in volume 2 of the Quartus II Handbook.
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Input delay from dual-purpose clock pin to fan-out destinations
Quartus II Logic Option
Cyclone IV Device Handbook, Volume 1
Area
6–5
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