EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 178
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Quantity
Price
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Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
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239
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8–12
Cyclone IV Device Handbook, Volume 1
1
EPCS1 does not support Cyclone IV devices because of its insufficient memory
capacity.
In configuration mode, the Cyclone IV device enables the serial configuration device
by driving the nCSO output pin low, which connects to the nCS pin of the
configuration device. The Cyclone IV device uses the DCLK and DATA[1]pins to send
operation commands and read address signals to the serial configuration device. The
configuration device provides data on its DATA pin, which connects to the DATA[0]
input of the Cyclone IV device.
All AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal
pull-up resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors.
The timing parameters for AS mode are not listed here because the t
t
PS mode shown in
Multi-Device AS Configuration
You can configure multiple Cyclone IV devices with a single serial configuration
device. When the first device captures all its configuration data from the bitstream, it
drives the nCEO pin low, enabling the next device in the chain. If the last device in the
chain is a Cyclone IV device, you can leave the nCEO pin of the last device
unconnected or use it as a user I/O pin after configuration. The nCONFIG, nSTATUS,
CONF_DONE, DCLK, and DATA[0] pins of each device in the chain are connected
together
STATUS
, t
CF2ST1
(Figure
, and t
8–3).
CD2UM
Table 8–10 on page
timing parameters are identical to the timing parameters for
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
8–35.
© December 2010 Altera Corporation
CF2CD
, t
CF2ST0
Configuration
, t
CFG
,
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