EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 396
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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3–6
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 4 of 6)
Cyclone IV Device Handbook, Volume 2
tx_preemp[4..0]
(1)
rx_eqctrl[3..0]
(1)
Port Name
Output
Input/
Input
Input
This is an optional pre-emphasis write control for the transmit buffer. Depending on what value
you set at this input, the controller dynamically writes the value to the pre-emphasis control
register of the transmit buffer.
The width of this signal is fixed to 5 bits if you enable either the Use 'logical_channel_address'
port for Analog controls reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the width of this signal is 5 bits per
channel.
tx_preemp[4..0]
00000
00001
00101
01001
01101
10000
10001
10010
10011
10100
10101
All other values => N/A
This is an optional write control to write an equalization control value for the receive side of the
PMA.
The width of this signal is fixed to 4 bits if you enable either the Use 'logical_channel_address'
port for Analog controls reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the width of this signal is 4 bits per
channel.
rx_eqctrl[3..0]
0001
0101
0111
All other values => N/A
0100
Corresponding ALTGX
Corresponding ALTGX instance settings
Low
Medium Low
High
Medium High
instance settings
13
16
17
18
19
20
21
0
1
5
9
Description
Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
© December 2010 Altera Corporation
emphasis setting (mA)
Corresponding pre-
Disabled
0.5
1.0
1.5
2.0
2.375
2.5
2.625
2.75
2.875
3.0
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