EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 331

IC CYCLONE IV FPGA 115K 780-FBGA

EP4CE115F29I8LN

Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er

Specifications of EP4CE115F29I8LN

Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
© December 2010 Altera Corporation
Figure 1–50. Example of Successful Receiver Detect Operation
Figure 1–51. Example of Unsuccessful Receiver Detect Operation
Electrical Idle Control
The Cyclone IV GX transceivers support transmitter buffer in electrical idle state
using the tx_forceelecidle port. During electrical idle, the transmitter buffer
differential and common mode output voltage levels are compliant to the PCIe Base
Specification 2.0 for Gen1 signaling rate.
Figure 1–52
port and the transmitter buffer output on the tx_dataout port.
Figure 1–52. Transmitter Buffer Electrical Idle State
Notes to
(1) The protocol requires the transmitter buffer to transition to a valid electrical idle after sending an electrical idle
(2) The protocol requires transmitter buffer to stay in electrical idle for a minimum of 20 ns for Gen1 signaling rate.
Signal Detect at Receiver
In PIPE mode, signal detection is supported with the built-in signal threshold
detection circuitry. When electrical idle inference is not enabled, the
rx_signaldetect signal is inverted and available as pipeelecidle port in the
PIPE interface.
ordered set within 8 ns.
tx_forcelecidle
Figure
tx_dataout
shows the relationship between assertion of the tx_forceelecidle
1–52:
tx_detectrxloopback
tx_detectrxloopback
pipephydonestatus
pipephydonestatus
powerdown[1..0]
powerdown[1..0]
pipestatus[2..0]
pipestatus[2..0]
<8 ns (1)
3'b000
2'b10(P1)
2'b10(P1)
3'b000
>20 ns (2)
3'b011
Cyclone IV Device Handbook, Volume 2
1–51

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