EP4CE115F29I8LN Altera, EP4CE115F29I8LN Datasheet - Page 86
EP4CE115F29I8LN
Manufacturer Part Number
EP4CE115F29I8LN
Description
IC CYCLONE IV FPGA 115K 780-FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE115F29I8LN
Number Of Logic Elements/cells
114480
Number Of Labs/clbs
7155
Total Ram Bits
3888000
Number Of I /o
528
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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5–24
Normal Mode
Cyclone IV Device Handbook, Volume 1
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the PLL fully compensates the delay introduced by the
GCLK network.
Figure 5–14
this mode.
Figure 5–14. Phase Relationship Between PLL Clocks in Normal Mode
Note to
(1) The external clock output can lead or lag the PLL internal clock signals.
Figure
5–14:
shows a waveform example of the phase relationship of the PLL clocks in
PLL Reference
Clock at the Input pin
PLL Clock at the
Register Clock Port
External PLL Clock
Outputs
(1)
Phase Aligned
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
Clock Feedback Modes
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