EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 10
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EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
1–8
Table 1–9. Bus Hold Parameters for Arria II GX Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Parameter
Bus-hold
low,
sustaining
current
Bus-hold
high,
sustaining
current
Bus-hold
low,
overdrive
current
Bus-hold
high,
overdrive
current
Bus-hold
trip point
Note to
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Table
Symbol
1–9:
I
V
I
I
I
SUSH
SUSL
ODL
ODH
TRIP
0 V < V
0 V < V
Table 1–8
Table 1–8. I/O Pin Leakage Current for Arria II GZ Devices
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–9
V
V
I
I
(max.)
(min.)
I
OZ
Cond.
IN
IN
Symbol
V
V
—
CCIO
CCIO
> V
< V
IN
IN
IL
IL
<
<
lists the Arria II GZ I/O pin leakage current specifications.
lists bus hold specifications for Arria II GX devices.
Input pin
Tri-stated I/O pin
Min
0.3
–8
—
—
8
1.2
Description
–125
Max
125
0.9
—
—
0.375 1.125
Min
–12
12
—
—
1.5
(Note 1)
–175
Max
175
V
V
—
—
I
O
= 0 V to V
= 0 V to V
Conditions
0.68
Min
–30
30
—
—
1.8
CCIOMAX
CCIOMAX
–200
1.07
Max
200
V
—
—
CCIO
(V)
Chapter 1: Device Datasheet for Arria II Devices
Min
–50
0.7
50
—
—
2.5
Min
–20
–20
–300
Max
300
1.7
—
—
December 2010 Altera Corporation
Min
–70
0.8
70
—
—
Typ
—
—
3.0
–500
Electrical Characteristics
Max
500
—
—
2
Max
20
20
Min
–70
0.8
70
—
—
3.3
–500
Max
500
Unit
—
—
µA
µA
2
Unit
µA
µA
µA
µA
V