EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 69
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EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 2 of 3)
December 2010 Altera Corporation
f
LVDS output data
rate)
f
(emulated
LVDS_E_3R
output data rate)
t
t
HSDR_TX
HSDR_TX_E3R
(7)
TX_JITTER
TX_DCD
Symbol
(true
(4)
SERDES factor,
SERDES factor,
SERDES factor,
True LVDS with
True LVDS with
DDR registers)
True LVDS and
True LVDS and
True LVDS and
SERDES (data
– 945 Mbps)
< 600 Mbps)
elements as
J = 2 (using
< 600 Mbps)
LVDS_E_3R
elements as
LVDS_E_3R
elements as
LVDS_E_3R
(using logic
(using SDR
Conditions
600–1,250
J = 4 to 10
J = 4 to 10
dedicated
(data rate
dedicated
(data rate
with logic
with logic
(data rate
SERDES)
and J = 1
emulated
emulated
emulated
register)
SERDES
SERDES
SERDES
rate 600
Mbps)
Min
—
—
—
—
45
(3)
(3)
(3)
I3
0.105
Max
0.16
945
945
175
260
55
(3)
Min
—
—
—
—
45
(3)
(3)
(3)
C4
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
0.105
0.16
Max
945
945
175
260
55
(3)
Min
—
—
(3)
(3)
(3)
—
—
45
C5,I5
0.135
0.18
Max
840
840
225
300
55
(3)
Min
—
—
—
—
45
(3)
(3)
(3)
C6
0.18
0.21
Max
740
740
300
350
55
(3)
Mbps
Mbps
Mbps
Unit
ps
UI
ps
UI
%
1–67