EPF10K130EQI240-2 Altera, EPF10K130EQI240-2 Datasheet - Page 53

IC FLEX 10KE FPGA 130K 240-PQFP

EPF10K130EQI240-2

Manufacturer Part Number
EPF10K130EQI240-2
Description
IC FLEX 10KE FPGA 130K 240-PQFP
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet

Specifications of EPF10K130EQI240-2

Number Of Logic Elements/cells
6656
Number Of Labs/clbs
832
Total Ram Bits
65536
Number Of I /o
186
Number Of Gates
342000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-MQFP, 240-PQFP
Family Name
FLEX 10KE
Number Of Usable Gates
130000
Number Of Logic Blocks/elements
6656
# Registers
186
# I/os (max)
186
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
6656
Ram Bits
65536
Device System Gates
342000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2206

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EPF10K130EQI240-2
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EPF10K130EQI240-2
Manufacturer:
ALTERA
0
Part Number:
EPF10K130EQI240-2
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPF10K130EQI240-2N
Manufacturer:
ALTERA
0
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Timing simulation and delay prediction are available with the Altera
Simulator and Timing Analyzer, or with industry-standard EDA tools.
The Simulator offers both pre-synthesis functional simulation to evaluate
logic design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
Figure 24
shows the overall timing model, which maps the possible paths
to and from the various elements of the FLEX 10KE device.
Figure 24. FLEX 10KE Device Timing Model
Dedicated
Interconnect
I/O Element
Clock/Input
Logic
Embedded Array
Element
Block
Figures 25
through
28
show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
Altera Corporation
53

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