EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 136
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
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I/O Structure
2–128
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
SSTL-2 class I and II
Table 2–33. Stratix II GX Supported I/O Standards
This I/O standard is only available on input and output column clock pins.
This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9,10, 11, and 12.
V
11, and 12).
1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
CCIO
I/O Standard
Table
is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10,
2–33:
f
Voltage-referenced
For more information on I/O standards supported by Stratix II GX I/O
banks, refer to the
Devices
Stratix II GX devices contain six I/O banks and four enhanced PLL
external clock output banks, as shown in
on the left of the device contain circuitry to support source-synchronous,
high-speed differential I/O for LVDS inputs and outputs. These banks
support all Stratix II GX I/O standards except PCI or PCI-X I/O pins, and
SSTL-18 class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
Type
chapter in volume 2 of the Stratix II GX Device Handbook.
Voltage (V
Selectable I/O Standards in Stratix II & Stratix II GX
Input Reference
1.25
REF
) (V)
Voltage (V
Output Supply
Figure
2.5
CCIO
2–87. The two I/O banks
) (V)
Altera Corporation
Board Termination
Voltage (V
October 2007
1.25
TT
) (V)
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