EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 73
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
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Altera Corporation
October 2007
R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between LABs, TriMatrix memory, DSP blocks, and
Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row
interconnects drive to other row or column interconnects at every fourth
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects. The
column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect.
These column resources include:
■
■
■
■
■
Stratix II GX devices include an enhanced interconnect structure in LABs
for routing shared arithmetic chains and carry chains for efficient
arithmetic functions. The register chain connection allows the register
output of one ALM to connect directly to the register input of the next
ALM in the LAB for fast shift registers. These ALM-to-ALM connections
bypass the local interconnect. The Quartus II Compiler automatically
takes advantage of these resources to improve utilization and
performance.
and register chain interconnects.
Shared arithmetic chain interconnects in a LAB
Carry chain interconnects in a LAB and from LAB to LAB
Register chain interconnects in a LAB
C4 interconnects traversing a distance of four blocks in an up and
down direction
C16 column interconnects for high-speed vertical routing through
the device
Figure 2–47
shows the shared arithmetic chain, carry chain,
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
2–65
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