EP2SGX30CF780C3N Altera, EP2SGX30CF780C3N Datasheet - Page 35
EP2SGX30CF780C3N
Manufacturer Part Number
EP2SGX30CF780C3N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1926
EP2SGX30CF780C3N
EP2SGX30CF780C3N
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Manufacturer
Quantity
Price
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Altera Corporation
October 2007
Figure 2–21. 8B/10B Decoder
The 8B/10B decoder in single-width mode translates the 10-bit encoded
data into the 8-bit equivalent data or control code. The 10-bit code
received must be from the supported Dx.y or Kx.y list with the proper
disparity or error flags asserted. All 8B/10B control signals, such as
disparity error or control detect, are pipelined with the data and
edge-aligned with the data.
decoded in the 8-bit data + 1-bit control indicator.
Figure 2–22. 8B/10B Decoder Conversion
The 8B/10B decoder in double-width mode translates the 20-bit
(2 × 10-bits) encoded code into the 16-bit (2 × 8-bits) equivalent data or
control code. The 20-bit upper and lower symbols received must be from
the supported Dx.y or Kx.y list with the proper disparity or error flags
To Byte
Deserializer
Parallel data
MSB received last
9
j
dataout[15..8]
Status Signals[1] (1)
dataout[7..0]
Status Signals[0]
h
8
H
7
g
7
G
6
(1)
Figure 2–22
8B/10B conversion
6
5
F
f
E
Stratix II GX Device Handbook, Volume 1
4
5
i
Decoder
Decoder
8B/10B
MSByte
8B/10B
LSByte
D
3
e
4
shows how the 10-bit symbol is
2
C
d
3
1
B
c
2
Stratix II GX Architecture
datain[19..10]
datain[9..0]
LSB received first
0
A
b
1
+
a
0
ctrl
From Rate
Matcher
2–27
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