EP2S60F672C5 Altera, EP2S60F672C5 Datasheet - Page 212
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EP2S60F672C5
Manufacturer Part Number
EP2S60F672C5
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1128
EP2S60F672C5ES
EP2S60F672C5ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5
Manufacturer:
SMARTLINK
Quantity:
8
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
5–76
Stratix II Device Handbook, Volume 1
Differential
SSTL-18 Class I
(3)
Differential
SSTL-18 Class II
(3)
1.8-V Differential
HSTL Class I
1.8-V Differential
HSTL Class II
1.5-V Differential
HSTL Class I
1.5-V Differential
HSTL Class II
3.3-V PCI
3.3-V PCI-X
LVDS
HyperTransport
technology
LVPECL
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5)
I/O Standard
(4)
(3)
(3)
(3)
(3)
Strength
10 mA
12 mA
16 mA
18 mA
20 mA
10 mA
12 mA
16 mA
18 mA
20 mA
10 mA
12 mA
16 mA
18 mA
20 mA
Drive
4 mA
6 mA
8 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
458
305
225
167
129
173
150
120
109
245
164
123
110
101
168
112
134
134
97
98
93
87
86
95
95
94
84
-3
-
-
-
Column I/O Pins
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
196
131
101
100
101
177
177
99
99
98
98
-4
-
-
-
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
196
131
101
100
101
177
177
99
99
98
98
-5
-
-
-
155
155
-3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(1)
(1)
Row I/O Pins
155
155
(1)
(1)
-4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
155
155
(1)
(1)
-5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Dedicated Clock Outputs
505
336
248
190
148
155
140
110
229
153
114
108
104
188
125
101
104
143
143
134
134
94
99
93
88
95
90
87
96
-3
-
Altera Corporation
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
196
131
101
100
101
177
177
134
134
99
99
98
98
-4
-
April 2011
570
380
282
220
175
206
160
130
127
282
188
140
124
110
104
102
196
131
101
100
101
177
177
134
134
99
99
98
98
-5
-