EP1S25F780C6 Altera, EP1S25F780C6 Datasheet - Page 198
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EP1S25F780C6
Manufacturer Part Number
EP1S25F780C6
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1121
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
10
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
246
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S25F780C6ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1S25F780C6N
Manufacturer:
ALTERA
Quantity:
1 045
Timing Model
4–28
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
EP1S10
EP1S20
EP1S25
EP1S30
SU
H
CO
LUT
CLR
PRE
CLKHL
Table 4–44. LE Internal Timing Microparameters
Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 1 of 2)
Device
Parameter
t
t
t
t
t
t
t
t
SU_R
SU_C
SU_R
SU_C
SU_R
SU_C
SU_R
SU_C
Symbol
1000
Min
100
100
100
10
t
t
t
t
C4
C8
C16
LOCAL
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
-5
76
176
76
76
276
276
76
176
Min
Max
156
366
-5
Delay for a C4 line with average loading; covers a distance of four
LAB rows.
Delay for a C8 line with average loading; covers a distance of eight
LAB rows.
Delay for a C16 line with average loading; covers a distance of 16
LAB rows.
Local interconnect delay, for connections within a LAB, and for the
final routing hop of connections to LABs, DSP blocks, RAM blocks
and I/Os.
Max
1111
Min
100
100
100
10
80
80
80
80
280
280
80
180
-6
Min
Max
176
459
-6
Max
1190
Min
114
114
114
11
80
80
80
80
280
280
80
180
Min
Parameter
-7
-7
Max
202
527
Max
1400
80
80
80
80
280
280
80
180
Min
135
135
135
13
Min
Altera Corporation
-8
-8
Max
Max
238
621
January 2006
ps
ps
ps
ps
ps
ps
ps
ps
Unit
Unit
ps
ps
ps
ps
ps
ps
ps