EP1S25F780C6 Altera, EP1S25F780C6 Datasheet - Page 96
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EP1S25F780C6
Manufacturer Part Number
EP1S25F780C6
Description
IC STRATIX FPGA 25K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S25F780C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
597
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1121
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
10
Company:
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA
Quantity:
246
Part Number:
EP1S25F780C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S25F780C6ES
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1S25F780C6N
Manufacturer:
ALTERA
Quantity:
1 045
PLLs & Clock Networks
2–82
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Table 2–18. Stratix Device PLL Availability
Device
PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.
PLLs 11 and 12 each have one single-ended output.
EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA
Table
v
v
v
v
v
v
v
2–18:
1
v
v
v
v
v
v
v
2
provide general purpose clocking with multiplication and phase shifting
as well as high-speed outputs for high-speed differential I/O support.
Enhanced and fast PLLs work together with the Stratix high-speed I/O
and advanced clock architecture to provide significant improvements in
system performance and bandwidth.
The Quartus II software enables the PLLs and their features without
requiring any external devices.
each Stratix device.
v
v
v
v
v
v
v
3
v
v
v
v
v
v
v
4
Fast PLLs
v
v
v
v
7
(3)
(3)
v
v
v
v
8
(3)
(3)
v
v
v
v
Table 2–18
9
(3)
(3)
v
v
v
v
10
(3)
(3)
shows the PLLs available for
5(1)
v
v
v
v
v
v
v
®
package.
Enhanced PLLs
6(1)
v
v
v
v
v
v
v
Altera Corporation
v(3) v(3)
11(2) 12(2)
v
v
July 2005
v
v