EP1SGX25CF672C6 Altera, EP1SGX25CF672C6 Datasheet - Page 122
EP1SGX25CF672C6
Manufacturer Part Number
EP1SGX25CF672C6
Description
IC STRATIX GX FPGA 25KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25CF672C6
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
455
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
455
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1SGX25CF672C6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1SGX25CF672C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1SGX25CF672C6ES
Manufacturer:
ALTERA
Quantity:
5
Digital Signal Processing Block
4–56
Stratix GX Device Handbook, Volume 1
Pipeline/Post Multiply Register
The output of 9
to pipeline multiply-accumulate and multiply-add/subtract functions.
For 36
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block
which consist of an adder/subtractor/accumulator unit, summation unit,
output select multiplexer, and output registers. The results are used to
configure the adder/output block as a pure output, accumulator, a simple
two-multiplier adder, four-multiplier adder, or final stage of the 36-bit
multiplier. You can configure the adder/output block to use output
registers in any mode, and must use output registers for the accumulator.
The system cannot use adder/output blocks independently of the
multiplier.
×
36-bit multipliers, this register pipelines the multiplier function.
Figure 4–33
×
9- or 18
shows the adder and output stages.
×
18-bit multipliers can optionally feed a register
Altera Corporation
February 2005