EP1SGX25CF672C6 Altera, EP1SGX25CF672C6 Datasheet - Page 184

• Manufacturer Part Number: EP1SGX25CF672C6
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Structure
4–118
Stratix GX Device Handbook, Volume 1
SSTL-3 class II
AGP (1
CTT
Table 4–28. I/O Support by Bank (Part 2 of 2)
×
I/O Standard
and 2
×
)
Each I/O bank has its own VCCIO pins. A single device can support 1.5-,
1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard
independently. Each bank also has dedicated VREF pins to support any
one of the voltage-referenced standards (such as SSTL-3) independently.
Each I/O bank can support multiple standards with the same V
input and output pins. Each bank can support one voltage-referenced
I/O standard. For example, when V
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix GX devices provide differential on-chip termination (LVDS I/O
standard) to reduce reflections and maintain signal integrity. Differential
on-chip termination simplifies board design by minimizing the number
of external termination resistors required. Termination can be placed
inside the package, eliminating small stubs that can still lead to
reflections. The internal termination is designed using transistors in the
linear region of operation.
Stratix GX devices support internal differential termination with a
nominal resistance value of 137.5 Ω for LVDS input receiver buffers.
LVPECL signals require an external termination resistor.
shows the device with differential termination.
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
Left Banks
(1 & 2)
v
v
CCIO
is 3.3 V, a bank can support
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
Altera Corporation
Figure 4–70
February 2005
v
v
v
CCIO
for