EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 118
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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I/O Structure
Figure 2–75. Stratix II GX Device Fast PLL
Notes to
(1)
(2)
(3)
(4)
I/O Structure
2–110
Stratix II GX Device Handbook, Volume 1
Clock
Input
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES)
circuitry. Stratix II GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O
support mode.
This signal is a differential I/O SERDES control signal.
Stratix II GX fast PLLs only support manual clock switchover.
Figure
Global or
regional clock (1)
Global or
regional clock (1)
4
2–75:
f
Shaded Portions of the
PLL are Reconfigurable
Circuitry (4)
Switchover
Clock
Refer to the
of the Stratix II GX Device Handbook for more information on enhanced
and fast PLLs. Refer to
on page 2–136
support.
The Stratix II GX IOEs provide many features, including:
■
■
■
■
■
■
■
■
■
■
■
■
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip termination for differential standards
Programmable pull-up during configuration
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
÷n
Frequency
Detector
Phase
PFD
PLLs in Stratix II & Stratix II GX Devices
for more information on high-speed differential I/O
Charge
Pump
“High-Speed Differential I/O with DPA Support”
Loop
Filter
÷m
VCO
VCO Phase Selection
Selectable at each PLL
Output Port
÷k
8
chapter in volume 2
Post-Scale
Counters
÷c0
÷c1
÷c2
÷c3
Altera Corporation
October 2007
4
4
8
8
diffioclk0
load_en0
load_en1
diffioclk1
Global clocks
Regional clocks
to DPA block
(2)
(3)
(3)
(2)
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