EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 304
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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JTAG Timing
Specifications
Figure 4–14
(1)
(1)
(2)
(3)
Table 4–115. DQS Bus Clock Skew Adder Specifications
(t
Table 4–116. DQS Phase Offset Delay Per Stage (ps)
DQS
This skew specification is the absolute maximum and minimum skew. For
example, skew on a 40 DQ group is 40 ps or 20 ps.
The delay settings are linear.
The valid settings for phase offset are -32 to +31.
The typical value equals the average of the minimum and maximum values.
Speed Grade
_CLOCK_SKEW_ADDER)
-3
-4
-5
18 DQ per DQS
36 DQ per DQS
4 DQ per DQS
9 DQ per DQS
shows the timing requirements for the JTAG signals
Mode
Min
Positive Offset
10
10
10
Max
15
15
16
DQS Clock Skew Adder (ps)
Min
Negative Offset
Notes
8
8
8
40
70
75
95
(1), (2),
Max
11
11
12
(1)
(3)
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