EP2SGX60EF1152C4N Altera, EP2SGX60EF1152C4N Datasheet - Page 27
![IC STRATIX II GX 60K 1152-FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP2SGX60EF1152C4N
Manufacturer Part Number
EP2SGX60EF1152C4N
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX60EF1152C4N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2183
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2SGX60EF1152C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
October 2007
The CRU has a built-in switchover circuit to select whether the PLL VCO
is aligned by the reference clock or the data. The optional port
rx_freqlocked monitors when the CRU is in locked-to-data mode.
In the automatic mode, the CRU PLL must be within the prescribed PPM
frequency threshold setting of the CRU reference clock for the CRU to
switch from locked-to-reference to locked-to-data mode.
The automatic switchover circuit can be overridden by using the optional
ports rx_locktorefclk and rx_locktodata.
possible combinations of these two signals.
If the rx_locktorefclk and rx_locktodata ports are not used, the
default is auto mode.
Deserializer (Serial-to-Parallel Converter)
The deserializer converts a serial bitstream into 8, 10, 16, or 20 bits of
parallel data. The deserializer receives the LSB first.
the deserializer.
Table 2–6. Receiver Lock Combinations
rx_locktodata
0
0
1
rx_locktorefclk
0
1
x
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
VCO (Lock to Mode)
Table 2–6
Reference clock
Figure 2–17
Auto
Data
shows the
shows
2–19
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