EP1S25F1020I6 Altera, EP1S25F1020I6 Datasheet - Page 268

no-image

EP1S25F1020I6

Manufacturer Part Number
EP1S25F1020I6
Description
IC STRATIX FPGA 25K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F1020I6

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
706
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
25660
# I/os (max)
706
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S25F1020I6
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EP1S25F1020I6
Manufacturer:
MOT
Quantity:
5 510
Part Number:
EP1S25F1020I6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S25F1020I6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S25F1020I6
Manufacturer:
ALTERA
0
Part Number:
EP1S25F1020I6
Manufacturer:
ALTERA
Quantity:
20 000
Part Number:
EP1S25F1020I6N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S25F1020I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S25F1020I6N
Manufacturer:
ALTERA
0
Part Number:
EP1S25F1020I6N
Manufacturer:
ALTERA
Quantity:
20 000
PLL Specifications
4–98
Stratix Device Handbook, Volume 1
t
t
f
f
t
t
t
t
t
t
t
f
EINJITTER
FCOMP
OUT
OUT_EXT
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 2 of 3)
Symbol
External feedback clock period jitter
External feedback clock
compensation time
Output frequency for internal global
or regional clock
Output frequency for external clock
(3)
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
(6)
Time required to reconfigure the
scan chains for PLLs 5 and 6
Time required to reconfigure the
scan chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale counters/delays)
(7) (11)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Parameter
(4)
(5)
(11)
Min
300
0.3
0.3
(9)
45
10
Typ
±20 mUI for <200-MHz outclk
±100 ps for >200-MHz outclk
289/f
193/f
±200
600
Max
357
369
100
400
55
SCANCLK
SCANCLK
22
6
(8)
(3)
Altera Corporation
January 2006
ps or
MHz
MHz
MHz
MHz
Unit
mUI
ps
ns
μs
μs
%

Related parts for EP1S25F1020I6