EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 260
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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High-Speed I/O Specification
High-Speed I/O
Specification
6–58
Stratix GX Device Handbook, Volume 1
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
HSTL class I
HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
t
f
t
C
HSCLK
RISE
Table 6–85. Stratix GX Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2] Pins (Part 2 of 2)
Table 6–86. High-Speed Timing Specifications & Definitions (Part 1 of 2)
High-Speed Timing Specification
I/O Standard
Table 6–86
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
provides high-speed timing specifications definitions.
-5 Speed Grade -6 Speed Grade -7 Speed Grade
400
250
225
225
400
225
717
420
350
200
200
167
167
150
150
150
150
250
400
400
300
717
420
300
350
167
167
150
150
133
133
133
133
225
225
225
225
350
350
350
250
225
717
717
420
420
Definitions
300
300
125
125
133
133
133
133
133
133
200
200
200
200
300
300
300
200
200
500
500
420
420
Altera Corporation
June 2006
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
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